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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. mos integrated circuit m m m m pd45256441, 45256841, 45256163 256m-bit synchronous dram 4-bank, lvttl document no. m13394ej3v0ds00 (3rd edition) date published april 1999 ns cp (k) printed in japan the mark h h h h shows major revised points. ? 1998 preliminary data sheet description the m pd45256441, 45256841, 45256163 are high-speed 268,435,456 bit synchronous dynamic random-access memories, organized as 16,777,216x4x4, 8,388,608x8x4, 4,194,304x16x4 (word x bit x bank), respectively. the synchronous drams achieved high-speed data transfer using the pipeline architecture. all inputs and outputs are synchronized with the positive edge of the clock. the synchronous drams are compatible with low voltage ttl (lvttl). these products are packaged in 54-pin tsop (ii). features fully synchronous dynamic ram, with all signals referenced to a positive clock edge pulsed interface possible to assert random column address in every cycle quad internal banks controlled by ba0 and ba1(bank select) byte control (x16) by ldqm and udqm programmable wrap sequence (sequential / interleave) programmable burst length (1, 2, 4, 8 and full page) programmable /cas latency (2 and 3) automatic precharge and controlled precharge cbr (auto) refresh and self refresh x4, x8, x16 organization single 3.3 v 0.3 v power supply lvttl compatible inputs and outputs 8,192 refresh cycles/64 ms burst termination by burst stop command and precharge command
preliminary data sheet m13394ej3v0ds00 2 m m m m pd 45256441, 45256841, 45256163 ordering information part number organization clock frequency package (word x bit x bank) mhz (max.) m pd45256441g5-a80-9jf 16m x 4 x 4 125 54-pin plastic tsop(ii) m pd45256441g5-a10-9jf 100 (400 mil) m pd45256441g5-a10b-9jf 100 m pd45256841g5-a80-9jf 8m x 8 x 4 125 m pd45256841g5-a10-9jf 100 m pd45256841g5-a10b-9jf 100 m pd45256163g5-a80-9jf 4m x 16 x 4 125 m pd45256163g5-a10-9jf 100 m pd45256163g5-a10b-9jf 100 m pd45256441g5-a80l-9jf 16m x 4 x 4 125 m pd45256441g5-a10l-9jf 100 m pd45256441g5-a10bl-9jf 100 m pd45256841g5-a80l-9jf 8m x 8 x 4 125 m pd45256841g5-a10l-9jf 100 m pd45256841g5-a10bl-9jf 100 m pd45256163g5-a80l-9jf 4m x 16 x 4 125 m pd45256163g5-a10l-9jf 100 m pd45256163g5-a10bl-9jf 100
preliminary data sheet m13394ej3v0ds00 3 m m m m pd 45256441, 45256841, 45256163 part number m pd45256841g5 - a80l interface 1 : lvttl number of banks 4 : 4bank organization 4 : x4 8 : x8 memory density 256 : 256m bits synchronous dram nec memory package g5 : tsop(ii) low voltage a : 3.3 0.3 v minimum cycle time 80 : 8 ns (125mhz) 10 : 10 ns (100mhz) 10b : 10 ns (100mhz) [ x4, x8 ] 163 [ x16 ] number of banks & interface 3 : 4bank, lvttl organization 16 : x16 low power
preliminary data sheet m13394ej3v0ds00 4 m m m m pd 45256441, 45256841, 45256163 pin configurations /xxx indicates active low si gnal. [ m m m m pd45256441] 54-pin plastic tsop(ii) (400mil) 16m word x 4 bit x 4 bank 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss nc v ss q nc dq3 v cc q nc nc v ss q nc dq2 v cc q nc v ss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 v ss v cc nc v cc q nc dq0 v ss q nc nc v cc q nc dq1 v ss q nc v cc nc /we /cas /ras /cs ba0 ba1 a10 a0 a1 a2 a3 v cc a0 to a12 note : address inputs ba0, ba1 : bank select dq0 to dq3 : data inputs/outputs clk : clock input cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable dqm : dq mask enable v cc : supply voltage v ss : ground v cc q : supply voltage for dq v ss q : ground for dq nc : no connection note a0 to a12 : row address inputs a0 to a9, a11 : column address inputs
preliminary data sheet m13394ej3v0ds00 5 m m m m pd 45256441, 45256841, 45256163 [ m m m m pd45256841] 54-pin plastic tsop(ii) (400mil) 8m word x 8 bit x 4 bank 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq7 v ss q nc dq6 v cc q nc dq5 v ss q nc dq4 v cc q nc v ss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 v ss v cc dq0 v cc q nc dq1 v ss q nc dq2 v cc q nc dq3 v ss q nc v cc nc /we /cas /ras /cs ba0 ba1 a10 a0 a1 a2 a3 v cc a0 to a12 note : address inputs ba0, ba1 : bank select dq0 to dq7 : data inputs/outputs clk : clock input cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable dqm : dq mask enable v cc : supply voltage v ss : ground v cc q : supply voltage for dq v ss q : ground for dq nc : no connection note a0 to a12 : row address inputs a0 to a9 : column address inputs
preliminary data sheet m13394ej3v0ds00 6 m m m m pd 45256441, 45256841, 45256163 [ m m m m pd45256163] 54-pin plastic tsop(ii) (400mil) 4m word x 16 bit x 4 bank 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v cc dq0 v cc q dq1 dq2 v ss q dq3 dq4 v cc q dq5 dq6 v ss q dq7 v cc ldqm /we /cas /ras /cs ba0 ba1 a10 a0 a1 a2 a3 v cc v ss dq15 v ss q dq14 dq13 v cc q dq12 dq11 v ss q dq10 dq9 v cc q dq8 v ss nc udqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 v ss a0 to a12 note : address inputs ba0, ba1 : bank select dq0 to dq15 : data inputs/outputs clk : clock input cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable ldqm : lower dq mask enable udqm : upper dq mask enable v cc : supply voltage v ss : ground v cc q : supply voltage for dq v ss q : ground for dq nc : no connection note a0 to a12 : row address inputs a0 to a8 : column address inputs
preliminary data sheet m13394ej3v0ds00 7 m m m m pd 45256441, 45256841, 45256163 block diagram clock generator mode register command decoder control logic row address buffer & refresh counter column address buffer & burst counter data control circuit latch circuit input & output buffer dq dqm clk cke address /cs /ras /cas /we bank d bank c bank b sense amplifier column decoder & latch circuit bank a row decoder
preliminary data sheet m13394ej3v0ds00 8 m m m m pd 45256441, 45256841, 45256163 contents 1. input/output pin function ..... 10 2. commands ..... 11 3. simplified state diagram ..... 14 4. truth table ..... 15 4.1 command truth table ..... 15 4.2 dqm truth table ..... 15 4.3 cke truth table ..... 15 4.4 operative command table ..... 16 4.5 command truth table for cke ..... 19 5. initialization ..... 20 6. programming the mode register ..... 21 7. mode register ..... 22 7.1 burst length and sequence ..... 23 8. address bits of bank-select and precharge ..... 24 9. precharge ..... 25 10. auto precharge ..... 26 10.1 read with auto precharge ..... 26 10.2 write with auto precharge ..... 27 11. read/write command interval ..... 28 11.1 read to read command interval ..... 28 11.2 write to write command interval ..... 28 11.3 write to read command interval ..... 29 11.4 read to write command interval ..... 30 12. burst termination ..... 31 12.1 burst stop command ..... 31 12.2 precharge termination ..... 32 12.2.1 precharge termination in read cycle ..... 32 12.2.2 precharge termination in write cycle ..... 33
preliminary data sheet m13394ej3v0ds00 9 m m m m pd 45256441, 45256841, 45256163 13. electrical specifications ..... 34 13.1 ac parameters for read timing ..... 39 13.2 ac parameters for write timing ..... 41 13.3 relationship between frequency and latency ..... 42 13.4 mode register set ..... 43 13.5 power on sequence and cbr (auto) refresh ..... 44 13.6 /cs function ..... 45 13.7 clock suspension during burst read (using cke function) ..... 46 13.8 clock suspension during burst write (using cke function) ..... 48 13.9 power down mode and clock mask ..... 50 13.10 cbr (auto) refresh ..... 51 13.11 self refresh (entry and exit) ..... 52 13.12 random column read (page with same bank) ..... 53 13.13 random column write (page with same bank) ..... 55 13.14 random row read (ping-pong banks) ..... 57 13.15 random row write (ping-pong banks) ..... 59 13.16 read and write ..... 61 13.17 interleaved column read cycle ..... 63 13.18 interleaved column write cycle ..... 65 13.19 auto precharge after read burst ..... 67 13.20 auto precharge after write burst ..... 69 13.21 full page read cycle ..... 71 13.22 full page write cycle ..... 73 13.23 byte write operation ..... 75 13.24 burst read and single write (option) ..... 76 13.25 full page random column read ..... 77 13.26 full page random column write ..... 78 13.27 pre (precharge) termination of burst ..... 79 14. package drawing ..... 81 15. recommended soldering conditions ..... 82 16. revision history ..... 82
preliminary data sheet m13394ej3v0ds00 10 m m m m pd 45256441, 45256841, 45256163 1. input/output pin function pin name input/output function clk input clk is the master clock input. other inputs signals are referenced to the clk rising edge. cke input cke determine validity of the next clk (clock). if cke is high, the next clk rising edge is valid; otherwise it is invalid. if the clk rising edge is invalid, the internal clock is not issued and the m pd45256 xxx sus pends operation. when the m pd45256 xxx is not in burst m ode and cke is negated, the device enters power down mode. during power down mode, cke must remain low. /cs input /cs low starts the command input cycle. when /cs is high, commands are ignored but operations continue. /ras, /cas, /we input /ras, /cas and /we have the same symbols on conventional dram but different functions. for details, refer to the command table. a0 - a10 input row address is determined by a0 - a12 at the clk (clock) rising edge in the active command cycle. it does not depend on the bit organization. column address is determined by a0 - a9, a11 at the clk rising edge in the read or write command cycle. it depends on the bit organization : a0 - a9, a11 for x4 device, a0 - a9 for x8 device, a0 - a8 for x16 device. a10 defines the precharge mode. when a10 is high in the precharge command cycle, all banks are precharged; when a10 is low, only the bank selected by ba0 and ba1 is precharged. when a10 is high in read or write command cycle, the precharge starts automatically after the burst access. ba0, ba1 input ba0 and ba1 are the bank select signal (bs). in command cycle, ba0 and ba1 low select bank a, ba0 low and ba1 high select bank b, ba0 high and ba1 low select bank c and then ba0 and ba1 high select bank d. dqm, udqm, ldqm input dqm controls i/o buffers. in x16 products, udqm and ldqm control upper byte and lower byte i/o buffers, respectively. in read mode, dqm controls the output buffers like a conventional /oe pin. dqm high and dqm low turn the output buffers off and on, respectively. the dqm latency for the read is two clo cks. in write mode, dqm controls the word mask. input data is written to the memory cell if dqm is low but not if dqm is high. the dqm latency for the write is zero. dq0 - dq15 input/output dq pins have the same function as i/o pins on a conventional dram. v cc , v ss , v cc q, v ss q (power supply) v cc and v ss are power supply pins for internal circuits. v cc q and v ss q are power supply pins for the output buffers.
preliminary data sheet m13394ej3v0ds00 11 m m m m pd 45256441, 45256841, 45256163 2. commands mode register set command (/cs, /ras, /cas, /we = low) the m pd45256 xxx has a m ode register that defines how the device operates. in this command, a0 through a12, ba0 and ba1 are the data input pins. after power on, the mode register set command must be executed to initialize the device. the mode register can be set only when all banks are in idle state. during 2 clk (t rsc ) following this command, the m pd45256 xxx c annot accept any other commands. fig.1 mode register set command /we /cas /ras /cs cke clk h add a10 ba0, ba1 activate command (/cs, /ras = low, /cas, /we = high) the m pd45256 xxx has four banks, each with 8,192 rows. this command activates the bank selected by ba0 and ba1 and a row address selected by a0 through a12. this command corresponds to a conventional dram's /ras falling. fig.2 row address strobe and bank activate command /we /cas /ras /cs cke clk h add a10 ba0, ba1 row row (bank select) precharge command (/cs, /ras, /we = low, /cas = high) this command begins precharge operation of the bank selected by ba0 and ba1. when a10 is high, all banks are precharged, regardless of ba0 and ba1. when a10 is low, only the bank selected by ba0 and ba1 is precharged. after this command, the m pd45256 xxx cant accept the activate command to the precharging bank during t rp (precharge to activate command period). this command corresponds to a conventional dram's /ras rising. fig.3 precharge command /we /cas /ras /cs cke clk h add a10 ba0, ba1 (bank select) (precharge select)
preliminary data sheet m13394ej3v0ds00 12 m m m m pd 45256441, 45256841, 45256163 write command (/cs, /cas, /we = low, /ras = high) if the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. the first write data in burst mode can input with this command with subsequent data on following clocks. fig.4 column address and write command /we /cas /ras /cs cke clk h add a10 ba0, ba1 (bank select) col. read command (/cs, /cas = low, /ras, /we = high) read data is available after /cas latency requirements have been met. this command sets the burst start address given by the column address. fig.5 column address and read command /we /cas /ras /cs cke clk h add a10 ba0, ba1 (bank select) col. cbr (auto) refresh command (/cs, /ras, /cas = low, /we, cke = high) this command is a request to begin the cbr (auto) refresh operation. the refresh address is generated internally. before executing cbr (auto) refresh, all banks must be precharged. after this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. during t rc period (from refresh command to refresh or activate command), the m pd45256 xxx c annot accept any other command. fig.6 auto refresh command add a10 ba0, ba1 /we /cas /ras /cs cke clk h (bank select)
preliminary data sheet m13394ej3v0ds00 13 m m m m pd 45256441, 45256841, 45256163 self refresh entry command (/cs, /ras, /cas, cke = low, /we = high) after the command execution, self refresh operation continues while cke remains low. when cke goes high, the m pd45256 xxx exits the self refresh mode. during self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. before executing self refresh, all banks must be precharged. fig.7 self refresh entry command /we /cas /ras /cs cke clk add a10 ba0, ba1 (bank select) burst stop command (/cs, /we = low, /ras, /cas = high) this command can stop the current burst operation. fig.8 burst stop command in full page mode /we /cas /ras /cs cke clk add a10 ba0, ba1 (bank select) h no operation (/cs = low, /ras, /cas, /we = high) this command is not a execution command. no operations begin or terminate by this command. fig.9 no operation /we /cas /ras /cs cke clk h add a10 ba0, ba1 (bank select)
preliminary data sheet m13394ej3v0ds00 14 m m m m pd 45256441, 45256841, 45256163 3. simplified state diagram cke cke cke cke cke cke cke cke precharge auto precharge pre read with auto precharge read bst bst pre (precharge termination) pre (precharge termination) act mrs ref cke cke self self exit idle mode register set cbr (auto) refresh row active self refresh power down active power down precharge read reada read suspend reada suspend write writea write suspend writea suspend power on write read automatic sequence manual input cke cke read write write with write
preliminary data sheet m13394ej3v0ds00 15 m m m m pd 45256441, 45256841, 45256163 4. truth table 4.1 command truth table function symbol cke /cs /ras /cas /we ba0, a10 a11, a12 n C 1 n ba1 a9 - a0 device deselect desl hxhxxxxx x no operation nop h x l h h h x x x burst stop bst h x l h h l x x x read read hxlhlhvl v read with auto precharge reada h x l h l h v h v write writ h x l h l l v l v write with auto precharge writa h x l h l l v h v bank activate act h x l l h h v v v precharge select bank pre h x l l h l v l x precharge all banks pall h x l l h l x h x mode register set mrs h x llllll v remark h = high level, l = low level, x = high or low level (don t care), v = valid data input 4.2 dqm truth table function symbol cke dq m n C 1 nul data write/output enable enb h x l data mask/output disable mask h x h upper byte write enable/output enable enbu h x l x lower byte write enable/output enable enbl h x x l upper byte write inhibit/output disable masku h x h x lower byte write inhibit/output disable maskl h x x h remark h = high level, l = low level, x = high or low level (don t care) 4.3 cke truth table current state function symbol cke /cs /ras /cas /we address n C 1 n activating clock suspend mode entry h l xxxxx any clock suspend l l xxxxx clock suspend clock suspend mode exit l h xxxxx idle cbr (auto) refresh command ref h h l l l h x idle self refresh entry selfhllllhx self refresh self refresh exit l h l h h h x lhhxxxx idle power down entry hlxxxxx power down power down exit l h h x x x x lhlhhhx remark h = high level, l = low level, x = high or low level (don t care) h h
preliminary data sheet m13394ej3v0ds00 16 m m m m pd 45256441, 45256841, 45256163 4.4 operative command table note 1 (1/3) current state /cs /ras /cas /we address command action notes idle h x x x x desl nop or power down 2 l h h x x nop or bst nop or power down 2 l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act row activating l l h l ba, a10 pre/pall nop l l l h x ref/self cbr (auto) refresh or self refresh 4 llllop-codemrs m ode register accessing row active h x x x x desl nop l h h x x nop or bst nop l h l h ba, ca, a10 read/reada begin read : determine ap 5 l h l l ba, ca, a10 writ/writa begin write : determine ap 5 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall precharge 6 lllhx ref/self illegal llllop-codemrs illegal read h x x x x desl continue burst to end ? row active l h h h x nop continue burst to end ? row active l h h l x bst burst stop ? row active l h l h ba, ca, a10 read/reada term burst, new read: determine ap 7 l h l l ba, ca, a10 writ/writa term burst, start write: determine ap 7, 8 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall term burst, precharging lllhx ref/self illegal llllop-codemrs illegal write hxxxx desl continue burst to end ? write recovering lhhhx nop continue burst to end ? write recovering l h h l x bst burst stop ? row active l h l h ba, ca, a10 read/reada term burst, start read: determine ap 7, 8 l h l l ba, ca, a10 writ/writa term burst, new write: determine ap 7 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall term burst, precharging 9 lllhx ref/self illegal llllop-codemrs illegal
preliminary data sheet m13394ej3v0ds00 17 m m m m pd 45256441, 45256841, 45256163 (2/3) current state /cs /ras /cas /we address command action notes read with auto h x x x x desl continue burst to end ? precharging precharge l h h h x nop continue burst to end ? precharging l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal 3 lllhx ref/self illegal llllop-codemrs illegal write with auto precharge h x x x x desl continue burst to end ? write recovering with auto precharge l h h h x nop continue burst to end ? write recovering with auto precharge l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal 3 lllhx ref/self illegal llllop-codemrs illegal precharging h x x x x desl nop ? enter idle after t rp lhhhx nop nop ? enter idle after t rp l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall nop ? enter idle after t rp lllhx ref/self illegal llllop-codemrs illegal row activating h x x x x desl nop ? enter bank active after t rcd lhhhx nop nop ? enter bank active after t rcd l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3, 10 l l h l ba, a10 pre/pall illegal 3 lllhx ref/self illegal llllop-codemrs illegal
preliminary data sheet m13394ej3v0ds00 18 m m m m pd 45256441, 45256841, 45256163 (3/3) current state /cs /ras /cas /we address command action notes write recovering h x x x x desl nop ? enter row active after t dpl lhhhx nop nop ? enter row active after t dpl l h h l x bst nop ? enter row active after t dpl l h l h ba, ca, a10 read/reada start read, determine ap 8 l h l l ba, ca, a10 writ/writa new write, determine ap l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal 3 lllhx ref/self illegal llllop-codemrs illegal write recovering h x x x x desl nop ? enter precharge after t dpl with auto precharge l h h h x nop nop ? enter precharge after t dpl l h h l x bst nop ? enter precharge after t dpl l h l h ba, ca, a10 read/reada illegal 3, 8 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal lllhx ref/self illegal llllop-codemrs illegal refreshing h x x x x desl nop ? enter idle after t rc l h h x x nop/bst nop ? enter idle after t rc l h l x x read/writ illegal l l h x x act/pre/pall illegal l l l x x ref/self/mrs illegal mode register h x x x x desl nop ? enter idle after t rsc accessing l h h h x nop nop ? enter idle after t rsc l h h l x bst illegal l h l x x read/writ illegal l l x x x act/pre/pall /ref/self/mr s illegal notes 1 all entries assume that cke was active (high level) during the preceding clock cycle. 2. if all banks are idle, and cke is inactive (low level), m pd45256 xxx w ill enter power down mode. all input buffers except cke will be disabled. 3. illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. 4. if all banks are idle, and cke is inactive (low level), m pd45256 xxx w ill enter self refresh mode. all input buffers except cke will be disabled. 5. illegal if t rcd is not satisfied. 6. illegal if t ras is not satisfied. 7. must satisfy burst interrupt condition. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. must mask preceding data which don't satisfy t dpl . 10. illegal if t rrd is not satisfied. remark h = high level, l = low level, x = high or low level (don t care), v = valid data
preliminary data sheet m13394ej3v0ds00 19 m m m m pd 45256441, 45256841, 45256163 4.5 command truth table for cke current state cke /cs /ras /cas /we address action notes n C1 n self refresh hxxxxxx invalid, clk(n C1 ) would exit s.r. (s.r.) l h h x x x x s.r. recovery lhlhhxx s.r. recovery lhlhl xx illegal l h l l x x x illegal llxxxxx maintain s.r. self refresh h h h x x x x idle after t rc recovery h h l h h x x idle after t rc h h l h l x x illegal h h l l x x x illegal hlhxxxx illegal h l l h h x x illegal h l l h l x x illegal hlllxxx illegal power downhxxxxx invalid, clk(n C1 ) would exit p.d. (p.d.) l h h x x x x exit p.d. ? idle lhlhhhx llxxxxx maintain power down mode all banks h h h x x x refer to operations in operative command table idle h h l h x x refer to operations in operative command table h h l l h x refer to operations in operative command table h h l l l h x cbr (auto) refresh hhllllop-coderefer to operations in operative command table h l h x x x refer to operations in operative command table h l l h x x refer to operations in operative command table h l l l h x refer to operations in operative command table hllllhx self refresh 1 hlllllop-coderefer to operations in operative command table lxxxxxx power down 1 row active hxxxxxx refer to operations in operative command table lxxxxxx power down 1 any state otherhhxxxx refer to operations in operative command table than listed h l xxxxx begin clock sus pend next cycle 2 above l h xxxxx exit clock sus pend next cycle llxxxxx maintain clock sus pend notes 1. self refresh can be entered only from the all banks idle state. power down can be entered only from all banks idle or row active state. 2. must be legal command as defined in operative command table. remark h = high level, l = low level, x = high or low level (don t care) h h
preliminary data sheet m13394ej3v0ds00 20 m m m m pd 45256441, 45256841, 45256163 5. initialization the synchronous dram is initialized in the power-on sequence according to the following. (1) to stabilize internal circuits, when power is applied, a 100 m s or longer pause must precede any signal toggling. (2) after the pause, all banks must be precharged using the precharge command (the precharge all banks command is convenient). (3) once the precharge is completed and the minimum t rp is satisfied, the mode register can be programmed. after the mode register set cycle, t rsc (2 clk minimum) pause must be satisfied as well. (4) two or more cbr (auto) refresh must be performed. remarks 1. the sequence of mode register programming and refresh above may be transposed. 2. cke and dqm must be held high until the precharge command is issued to ensure data-bus hi-z.
preliminary data sheet m13394ej3v0ds00 21 m m m m pd 45256441, 45256841, 45256163 6. programming the mode register the mode register is programmed by the mode register set command using address bits a12 through a0, ba0 and ba1 as data inputs. the register retains data until it is reprogrammed or the device loses power. the mode register has four fields; options : a12 through a7, ba0, ba1 /cas latency : a6 through a4 wrap type : a3 burst length : a2 through a0 following mode register programming, no command can be issued before at least 2 clk have elapsed. /cas latency /cas latency is the most critical of the parameters being set. it tells the device how many clocks must elapse before the data will be available. the value is determined by the frequency of the clock and the speed grade of the device. 13.3 relationship between frequency and latency shows the relationship of /cas latency to the clock period and the speed grade of the device. burst length burst length is the number of words that will be output or input in a read or write cycle. after a read burst is completed, the output bus will become hi-z. the burst length is programmable as 1, 2, 4, 8 or full page. wrap type (burst sequence) the wrap type specifies the order in which the burst data will be addressed. this order is programmable as either sequential or interleave. the method chosen will depend on the type of cpu in the system. some microprocessor cache system are optimized for sequential addressing and others for interleaved addressing. 7.1 burst length and sequence shows the addressing sequence for each burst length using them. both sequences support bursts of 1, 2, 4 and 8. additionally, sequence supports the full page length.
preliminary data sheet m13394ej3v0ds00 22 m m m m pd 45256441, 45256841, 45256163 7. mode register wt = 1 1 2 4 8 r r r r 1 0 0 0 0 a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 ba0 jedec standard test set (refresh counter test) bl wt ltmode 0 0 1 x x a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 ba0 burst read and single write (for write through cache) 0 1 a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 ba0 use in future v v v v v v 1v 1 x x x a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 ba0 vender specific bl wt ltmode 0 0 0 0 0 a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 ba0 mode register set v = valid x = don t care wt = 0 1 2 4 8 r r r full page bits2-0 000 001 010 011 100 101 110 111 burst length sequential interleave 0 1 wrap type /cas latency r r 2 3 r r r r bits6-4 000 001 010 011 100 101 110 111 latency mode 0 ba1 x ba1 ba1 x ba1 0 ba1 remark r : reserved mode register set timing clk cke /cs /ras /cas /we a0 - a10, ba0, ba1 mode register set
preliminary data sheet m13394ej3v0ds00 23 m m m m pd 45256441, 45256841, 45256163 7.1 burst length and sequence [burst of two] starting address (column address a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 [burst of four] starting address (column address a1 - a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 [burst of eight] starting address (column address a2 - a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 full page burst is an extension of the above tables of sequential addressing, with the length being 2,048 (for 64m x4 device), 1,024 (for 32m x8 device), 512 (for 16m x16 device).
preliminary data sheet m13394ej3v0ds00 24 m m m m pd 45256441, 45256841, 45256163 8. address bits of bank-select and precharge a11 a10 a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 row (activate command) a11 a10 a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 (precharge command) disables auto-precharge (end of burst) 0 enables auto-precharge (end of burst) 1 a11 a10 a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 col. (/cas strobes) x : dont care ba0 ba1 ba0 ba1 ba0 ba1 select bank a activate command 0 select bank b activate command 0 1 1 0 1 0 1 ba0 ba1 result select bank c activate command select bank d activate command enables read/write commands for bank a 0 enables read/write commands for bank b 0 1 1 0 1 0 1 ba0 ba1 result enables read/write commands for bank c enables read/write commands for bank d result precharge bank a precharge bank b precharge bank c precharge bank d precharge all banks a10 0 0 0 0 1 ba0 0 0 1 1 x ba1 0 1 0 1 x a12 a12 a12
preliminary data sheet m13394ej3v0ds00 25 m m m m pd 45256441, 45256841, 45256163 9. precharge the precharge command can be issued anytime after t ras(min.) is satisfied. soon after the precharge command is issued, precharge operation performed and the synchronous dram enters the idle state after t rp is satisfied. the parameter t rp is the time required to perform the precharge. the earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. it is depending on the /cas latency and clock cycle time. t0 t1 t2 t3 t4 t5 t6 t7 burst length=4 read read q1 q2 q3 q4 pre hi-z q1 q2 q3 q4 pre hi-z (t ras must be satisfied) clk command /cas latency = 2 dq command /cas latency = 3 dq t8 in order to write all data to the memory cell correctly, the asynchronous parameter t dpl must be satisfied. the t dpl(min.) specification defines the earliest time that a precharge command can be issued. minimum number of clocks is calculated by dividing t dpl (min.) with clock cycle time. in summary, the precharge command can be issued relative to reference clock that indicates the last data word is valid. in the following table, minus means clocks before the reference; plus means time after the reference /cas latency read write 2C1+t dpl(min.) 3C2+t dpl(min.)
preliminary data sheet m13394ej3v0ds00 26 m m m m pd 45256441, 45256841, 45256163 10. auto precharge during a read or write command cycle, a10 controls whether auto precharge is selected. a10 high in the read or write command (read with auto precharge command or write with auto precharge command), auto precharge is selected and begins automatically. the t ras must be satisfied with a read with auto precharge or a write with auto precharge operation. in addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. in read cycle, once auto precharge has started, an activate command to the bank can be issued after t rp has been satisfied. in write cycle, the t dal must be satisfied to issue the next activate command to the bank being precharged. the timing that begins the auto precharge cycle depends on both the /cas latency programmed into the mode register and whether read or write cycle. 10.1 read with auto precharge during a read cycle, the auto precharge begins one clock earlier (/cas latency of 2) or two clocks earlier (/cas latency of 3) the last data word output. qb1 qb2 qb3 qb4 auto precharge starts reada b hi-z qb1 qb2 qb3 qb4 auto precharge starts reada b hi-z dq command dq command /cas latency = 2 /cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 (t ras must be satisfied) t9 remark reada means read with auto precharge
preliminary data sheet m13394ej3v0ds00 27 m m m m pd 45256441, 45256841, 45256163 10.2 write with auto precharge during a write cycle, the auto precharge starts at the timing that is equal to the value of the t dpl(min.) after the last data word input to the device. db1 db2 db3 db4 auto precharge starts writa b hi-z db1 db2 db3 db4 auto precharge starts writa b hi-z dq command dq command /cas latency = 2 /cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 (t ras must be satisfied) t dpl(min.) t dpl(min.) remark writa means write with auto precharge in summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid. in the table below, minus means clocks before the reference; plus means after the reference. /cas latency read write 2C1+t dpl(min.) 3C2+t dpl(min.)
preliminary data sheet m13394ej3v0ds00 28 m m m m pd 45256441, 45256841, 45256163 11. read/write command interval 11.1 read to read command interval during a read cycle, when new read command is issued, it will be effective after /cas latency, even if the previous read operation does not completed. read will be interrupted by another read. the interval between the commands is 1 cycle minimum. each read command can be issued in every clock without any restriction. qb1 qb2 qb3 qb4 hi-z read a dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4, /cas latency = 2 read b qa1 1cycle t9 11.2 write to write command interval during a write cycle, when a new write command is issued, the previous burst will terminate and the new burst will begin with a new write command. write will be interrupted by another write. the interval between the commands is minimum 1 cycle. each write command can be issued in every clock without any restriction. db1 db2 db3 db4 hi-z write a dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4, /cas latency = 2 write b da1 1cycle
preliminary data sheet m13394ej3v0ds00 29 m m m m pd 45256441, 45256841, 45256163 11.3 write to read command interval write command and read command interval is also 1 cycle. only the write data before read command will be written. the data bus must be hi-z at least one cycle prior to the first d out . qb1 qb2 qb3 qb4 write a hi-z qb1 qb2 qb3 qb4 write a hi-z dq command dq command /cas latency = 2 /cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 da1 da1 read b read b
preliminary data sheet m13394ej3v0ds00 30 m m m m pd 45256441, 45256841, 45256163 11.4 read to write command interval during a read cycle, read can be interrupted by write. the read and write command interval is 1 cycle minimum. there is a restriction to avoid data conflict. the data bus must be hi-z using dqm before write. d1 d2 d3 d4 read dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 write dqm hi-z 1cycle read can be interrupted by write. dqm must be high at least 3 clocks prior to the write command. clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 8 t9 q1 q2 q3 read dq command d1 d2 d3 write dqm hi-z is necessary q1 q2 read dq command d1 d2 d3 write dqm hi-z is necessary /cas latency = 2 /cas latency = 3
preliminary data sheet m13394ej3v0ds00 31 m m m m pd 45256441, 45256841, 45256163 12. burst termination there are two methods to terminate a burst operation other than using a read or a write command. one is the burst stop command and the other is the precharge command. 12.1 burst stop command during a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to hi-z after the /cas latency from the burst stop command. read command clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x q1 q2 q3 dq /cas latency = 2 hi-z q1 q2 q3 dq /cas latency = 3 hi-z bst remark bst : burst stop command during a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to hi-z at the same clock with the burst stop command. d2 d3 d4 write dq command /cas latency = 2, 3 clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x bst hi-z d1 remark bst: burst stop command
preliminary data sheet m13394ej3v0ds00 32 m m m m pd 45256441, 45256841, 45256163 12.2 precharge termination 12.2.1 precharge termination in read cycle during a read cycle, the burst read operation is terminated by a precharge command. when the precharge command is issued, the burst read operation is terminated and precharge starts. the same bank can be activated again after t rp from the precharge command. to issue a precharge command, t ras must be satisfied. when /cas latency is 2, the read data will remain valid until one clock after the precharge command. read clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 2 q1 dq command q2 q3 q4 act t rp pre hi-z (t ras must be satisfied) when /cas latency is 3, the read data will remain valid until two clocks after the precharge command. read clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 3 dq command q1 q2 q3 act t rp pre hi-z t8 q4 (t ras must be satisfied)
preliminary data sheet m13394ej3v0ds00 33 m m m m pd 45256441, 45256841, 45256163 12.2.2 precharge termination in write cycle during a write cycle, the burst write operation is terminated by a precharge command. when the precharge command is issued, the burst write operation is terminated and precharge starts. the same bank can be activated again after t rp from the precharge command. to issue a precharge command, t ras must be satisfied. when /cas latency is 2, the write data written prior to the precharge command will be correctly stored. however, invalid data may be written at the same clock as the precharge command. to prevent this from happening, dqm must be high at the same clock as the precharge command. this will mask the invalid data. write clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 2 dq command d1 d2 d3 act dqm t rp pre hi-z d4 d5 (t ras must be satisfied) when /cas latency is 3, the write data written prior to the precharge command will be correctly stored. however, invalid data may be written at the same clock as the precharge command. to prevent this from happening, dqm must be high at the same clock as the precharge command. this will mask the invalid data. write clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 3 dq command d1 d2 d3 act dqm t rp pre hi-z d5 t8 d4 (t ras must be satisfied)
preliminary data sheet m13394ej3v0ds00 34 m m m m pd 45256441, 45256841, 45256163 13. electrical specifications all voltages are referenced to v ss (gnd). after power up, wait more than 100 m s and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. absolute maximum ratings parameter symbol condition rating unit voltage on power supply pin relative to gnd v cc , v cc q C0.5 to +4.6 v voltage on input pin relative to gnd v t C0.5 to +4.6 v short circuit output current i o 50 ma power dissipation p d 1w operating ambient temperature t a 0 to +70 c storage temperature t stg C55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc , v cc q 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc +0.3 note1 v low level input voltage v il - 0.3 note2 +0.8 v operating ambient temperature t a 070 c notes 1. v ih(max.) = v cc + 1.5 v (pulse width 5 ns) 2. v il(min.) = C1.5 v (pulse width 5 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i1 a0 - a12, ba0, ba1 2.5 4 pf c i2 clk, cke, /cs, /ras, /cas, /we, dqm, udqm, ldqm 2.5 4 data input/output capacitance c i/o dq0 - dq15 4 6.5 pf
preliminary data sheet m13394ej3v0ds00 35 m m m m pd 45256441, 45256841, 45256163 dc characteristics 1 (recommended operating conditions unless otherwise noted) parameter symbol test condition /cas grade maximum. unit notes latency x4 x8 x16 operating current i cc1 burst length = 1 cl=2 -a80 120 120 130 ma 1 t rc 3 t rc(min.) -a10 120 120 130 i o = 0 ma -a10b 110 120 130 one bank active cl=3 -a80 125 125 135 -a10 125 125 135 -a10b 115 125 135 precharge standby current i cc2 p cke v il(max.) , t ck = 15 ns 1 1 1 ma in power down mode i cc2 ps cke v il(max.) , t ck = 111 precharge standby current in non power down mode i cc2 ncke 3 v ih(min.) , t ck = 15 ns, /cs 3 v ih(min.) , input signals are changed one time during 30 ns. 15 15 15 ma i cc2 ns cke 3 v ih(min.) , t ck = , input signals are stable. 6 6 6 active standby current in i cc3 p cke v il(max.) , t ck = 15 ns 3 3 3 ma power down mode i cc3 ps cke v il(max.) , t ck = 222 active standby current in non power down mode i cc3 ncke 3 v ih(min.) , t ck = 15 ns, /cs 3 v ih(min.) input signals are changed one time during 30 ns. 25 25 25 ma i cc3 ns cke 3 v ih(min.) , t ck = , input signals are stable. 15 15 15 operating current i cc4 t ck 3 t ck(min.) cl=2 -a80 105 120 145 ma 2 (burst mode) i o = 0 ma -a10 85 95 110 all banks active -a10b 75 85 100 cl=3 -a80 130 145 175 -a10 110 125 140 -a10b 110 125 140 cbr (auto) refresh current i cc5 t rc 3 t rc(min.) cl=2 -a80 230 230 230 ma 3 -a10 230 230 230 -a10b 220 220 220 cl=3 -a80 240 240 240 -a10 240 240 240 -a10b 230 230 230 self refresh current i cc6 cke 0.2 v-**333ma -**l 1.4 1.4 1.4 notes 1. i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc1 is measured on condition that addresses are changed only one time during t ck(min.) . 2 .i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck(min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck(min.) . h
preliminary data sheet m13394ej3v0ds00 36 m m m m pd 45256441, 45256841, 45256163 dc characteristics 2 (recommended operating conditions unless otherwise noted) parameter symbol test condition min. typ. max. unit notes input leakage current i i(l) 0 v i v cc q, v cc q = v cc , all other pins not under test = 0 v C1.0 +1.0 m a output leakage current i o(l) 0 v o v cc q, d out is disabled C1.5 +1.5 m a high level output voltage v oh i o = C 4 ma 2.4 v low level output voltage v ol i o = + 4 ma 0.4 v ac characteristics (recommended operating conditions unless otherwise noted) test conditions ac measurements assume t t = 1 ns. reference level for measuring timing of input signals is 1.4 v. transition times are measured between v ih and v il . if t t is longer than 1 ns, reference level for measuring timing of input signals is v ih(min.) and v il(max.) . an access time is measured at 1.4 v. t ck t ch t cl 2.0 v 1.4 v 0.8 v clk 2.0 v 1.4 v 0.8 v input t setup t hold output t ac t oh
preliminary data sheet m13394ej3v0ds00 37 m m m m pd 45256441, 45256841, 45256163 synchronous characteristics parameter symbol -80 -10 -10b unit note min. max. min. max. min. max. clock cycle time /cas latency = 3 t ck3 8 (125mhz) 10 (100 mhz) 10 (100 mhz) ns /cas latency = 2 t ck2 10 (100 mhz) 13 (77 mhz) 15 (67 mhz) ns access time from clk /cas latency = 3 t ac3 667ns1 /cas latency = 2 t ac2 678ns1 clk high level width t ch 333.5ns clk low level width t cl 333.5ns data-out hold time t oh 333ns1 data-out low-impedance time t lz 000ns data-out high-impedance time /cas latency = 3 t hz3 363637ns /cas latency = 2 t hz2 363738ns data-in setup time t ds 222.5ns data-in hold time t dh 111ns address setup time t as 222.5ns address hold time t ah 111ns cke setup time t cks 222.5ns cke hold time t ckh 111ns cke setup time (power down exit) t cksp 222.5ns command (/cs, /ras, /cas, /we, dqm) setup time t cms 222.5ns command (/cs, /ras, /cas, /we, dqm) hold time t cmh 111ns note 1. output load output z = 50 w 50 pf h
preliminary data sheet m13394ej3v0ds00 38 m m m m pd 45256441, 45256841, 45256163 asynchronous characteristics parameter symbol -80 -10 -10b unit note min. max. min. max. min. max. act to ref/act command period (operation) t rc 70 70 90 ns ref to ref/act command period (refresh) t rc1 70 78 90 ns act to pre command period t ras 48 120,000 50 120,000 60 120,000 ns pre to act command period t rp 20 20 30 ns delay time act to read/write command t rcd 20 20 30 ns act(one) to act(another) command period t rrd 16 20 20 ns data-in to pre command period t dpl 81010ns data-in to act(ref) command /cas latency = 3 t dal3 1clk+20 1clk+20 1clk+30 ns period (auto precharge) /cas latency = 2 t dal2 1clk+20 1clk+20 1clk+30 ns mode register set cycle time t rsc 222clk transition time t t 0.5 30 1 30 1 30 ns refresh time (8,192 refresh cycles) t ref 64 64 64 ms
preliminary data sheet m13394ej3v0ds00 39 m m m m pd 45256441, 45256841, 45256163 13.1 ac parameters for read timing (manual precharge, burst length = 4, /cas latency = 3) t oh t lz t ac t oh t ac t ac t oh t oh t ac t hz t ras t rc ba0 t ckh t rp t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 clk cke /cs /ras /cas /we ba1 a10 add dqm dq t rcd t cks t ch t cl t ck t cms t cmh t as t ah l hi-z activate command for bank a precharge command for bank a read command for bank a activate command for bank a
preliminary data sheet m13394ej3v0ds00 40 m m m m pd 45256441, 45256841, 45256163 ac parameters for read timing (auto precharge, burst length = 4, /cas latency = 3) t oh t lz t ac t oh t ac t ac t oh t oh t ac t hz t ras t rrd t rc ba0 t ckh t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 clk cke /cs /ras /cas /we ba1 a10 add dqm dq t rcd t cks t ch t cl t ck t cms t cmh t as t ah l hi-z auto precharge start for bank c activate command for bank c activate command for bank d read with auto precharge command for bank c activate command for bank c
preliminary data sheet m13394ej3v0ds00 41 m m m m pd 45256441, 45256841, 45256163 13.2 ac parameters for write timing (burst length = 4, /cas latency = 3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke ba0 a10 add dqm dq hi-z t as t ah t ds t dh t rcd t dal t rc t rrd t rcd t ras t rc t dpl t rp t ckh t cms t cmh t cks /cs /ras /cas /we ba1 auto precharge start for bank c l activate command for bank c activate command for bank b write command for bank b activate command for bank b write with auto precharge command for bank c precharge command for bank b activate command for bank c
preliminary data sheet m13394ej3v0ds00 42 m m m m pd 45256441, 45256841, 45256163 13.3 relationship between frequency and latency speed version -80 -10 -10b clock cycle time [ns] 8 10 10 13 10 15 frequency [mhz] 125 100 100 77 100 67 /cas latency 323232 [t rcd ] 322232 /ras latency (/cas latency + [t rcd ]) 645464 [t rc ] 977696 [t rc1 ] 978696 [t ras ] 655464 [t rrd ] 222222 [t rp ] 322232 [t dpl ] 111111 [t dal ] 433343 [t rsc ] 222222
preliminary data sheet m13394ej3v0ds00 43 m m m m pd 45256441, 45256841, 45256163 13.4 mode register set (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq ba1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 hi-z address key t rp precharge all banks command mode register set command activate command is valid h t rsc 2 clk (min.)
preliminary data sheet m13394ej3v0ds00 44 m m m m pd 45256441, 45256841, 45256163 13.5 power on sequence and cbr (auto) refresh clk cke /cs /ras /cas /we ba1 a10 add dqm dq hi-z t rsc address key t rp high level is necessary high level is necessary clock signal is necessary 2 refresh cycles are necessary t rc1 t rc1 precharge all banks command is necessary mode register set command is necessary cbr (auto) refresh command is necessary activate command refresh command is necessary ba0
preliminary data sheet m13394ej3v0ds00 45 m m m m pd 45256441, 45256841, 45256163 13.6 /cs function (at 100 mhz, burst length = 4, /cas latency = 3) only /cs signal needs to be issued at minimum rate clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h l hi-z l ba0 l raa qaa1 qaa2 qaa3 qaa4 dab1 dab2 dab3 dab4 activate command for bank a read command for bank a write command for bank a precharge command for bank a raa caa cab
preliminary data sheet m13394ej3v0ds00 46 m m m m pd 45256441, 45256841, 45256163 13.7 clock suspension during burst read (using cke function) (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 caa ba0 l hi-z raa raa activate command for bank a read command for bank a 1-clock suspended 2-clock suspended 3-clock suspended hi-z (turn off) at the end of burst
preliminary data sheet m13394ej3v0ds00 47 m m m m pd 45256441, 45256841, 45256163 clock suspension during burst read (using cke function) (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 caa ba0 l hi-z raa raa activate command for bank a read command for bank a 1-clock suspended 2-clock suspended 3-clock suspended hi-z (turn off) at the end of burst
preliminary data sheet m13394ej3v0ds00 48 m m m m pd 45256441, 45256841, 45256163 13.8 clock suspension during burst write (using cke function) (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 caa ba0 l hi-z raa raa daa1 daa2 daa3 daa4 activate command for bank a 1-clock suspended 2-clock suspended 3-clock suspended write command for bank a
preliminary data sheet m13394ej3v0ds00 49 m m m m pd 45256441, 45256841, 45256163 clock suspension during burst write (using cke function) (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 caa ba0 l hi-z raa raa daa1 daa2 daa3 daa4 activate command for bank a 1-clock suspended 2-clock suspended 3-clock suspended write command for bank a
preliminary data sheet m13394ej3v0ds00 50 m m m m pd 45256441, 45256841, 45256163 13.9 power down mode and clock mask (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa3 caa l hi-z raa ba0 t cksp t cksp qaa1 qaa2 valid activate command for bank a power down mode entry active standby power down mode exit read command for bank a clock mask start clock mask end power down mode entry precharge command for bank a precharge standby power down mode exit qaa4 raa h
preliminary data sheet m13394ej3v0ds00 51 m m m m pd 45256441, 45256841, 45256163 13.10 cbr (auto) refresh clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 tn tn + 1tn + 2tn + 3tn + 4tn + 5tn + 6tmtm + 1tm + 2tm + 3tm + 4tm + 5tm + 6tm + 7 ba0 l hi-z t rp h t rc1 t rc1 q1 precharge command (if necessary) cbr (auto) refresh cbr(auto) refresh activate command read command
preliminary data sheet m13394ej3v0ds00 52 m m m m pd 45256441, 45256841, 45256163 13.11 self refresh (entry and exit) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 tn tn + 1tn + 2tmtm + 1 tk tk + 1 tk + 2tk + 3tk + 4 t rp t rc1 t rc1 ba0 precharge command (if necessary) self refresh entry self refresh exit next clock enable self refresh entry (or activate command) activate command self refresh exit next clock enable l hi-z
preliminary data sheet m13394ej3v0ds00 53 m m m m pd 45256441, 45256841, 45256163 13.12 random column read (page with same bank) (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 qad1 qad2 qad3 h rad raa cad cac caa rad cab ba0 raa precharge command for bank a activate command for bank a read command for bank a read command for bank a read command for bank a activate command for bank a read command for bank a l hi-z
preliminary data sheet m13394ej3v0ds00 54 m m m m pd 45256441, 45256841, 45256163 random column read (page with same bank) (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba1 a10 add dqm dq precharge command for bank a activate command for bank a read command for bank a read command for bank a read command for bank a activate command for bank a read command for bank a t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 h raa raa caa cac caa raa cab ba0 raa l hi-z
preliminary data sheet m13394ej3v0ds00 55 m m m m pd 45256441, 45256841, 45256163 13.13 random column write (page with same bank) (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z dda1 dda2 dda3 dda4 ddb1 ddb2 ddc1 ddc2 ddc3 ddc4 ddd1 ddd2 ddd3 h rdd rda cdd cdc cda rdd cdb ba0 rda ddd4 activate command for bank d write command for bank d write command for bank d write command for bank d precharge command for bank d activate command for bank d write command for bank d
preliminary data sheet m13394ej3v0ds00 56 m m m m pd 45256441, 45256841, 45256163 random column write (page with same bank) (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z dda1 dda2 dda3 dda4 ddb1 ddb2 ddc1 ddc2 ddc3 ddc4 h rdd rda cdd cdc cda rdd cdb ba0 rda ddd1 activate command for bank d write command for bank d write command for bank d write command for bank d precharge command for bank d activate command for bank d write command for bank d ddd2
preliminary data sheet m13394ej3v0ds00 57 m m m m pd 45256441, 45256841, 45256163 13.14 random row read (ping-pong banks) (1/2) (burst length = 8, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z qda1 qda2 qda3 qda4 qda5 qda6 qda7 qda8 qba1 qba2 qba3 qba4 qba5 h rdb rda cdb cba cda rdb rba rda ba0 rba qba6 qba7 qba8 activate command for bank d read command for bank d activate command for bank b read command for bank b precharge command for bank d activate command for bank d read command for bank d
preliminary data sheet m13394ej3v0ds00 58 m m m m pd 45256441, 45256841, 45256163 random row read (ping-pong banks) (2/2) (burst length = 8, /cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z qba1 qba2 qba3 qba4 qba5 qba6 qba7 qba8 qaa1 qaa2 qaa3 qaa4 qaa5 h rbb rba cbb caa cba rbb raa rba raa qaa6 qaa7 ba1 activate command for bank b read command for bank b activate command for bank a read command for bank a precharge command for bank b activate command for bank b read command for bank b precharge command for bank a
preliminary data sheet m13394ej3v0ds00 59 m m m m pd 45256441, 45256841, 45256163 13.15 random row write (ping-pong banks) (1/2) (burst length = 8, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z daa5 daa6 daa7 daa8 dda1 dda2 dda3 dda4 dda5 dda6 dda7 dda8 dab1 h raa cab cda caa rda raa rda dab2 dab3 ba0 rab rab daa1 daa2 daa3 daa4 activate command for bank a write command for bank a write command for bank d activate command for bank d precharge command for bank a activate command for bank a write command for bank a precharge command for bank d
preliminary data sheet m13394ej3v0ds00 60 m m m m pd 45256441, 45256841, 45256163 random row write (ping-pong banks) (2/2) (burst length = 8, /cas latency = 3) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 daa3 daa4 daa5 daa6 daa7 daa8 dda1 dda2 dda3 dda5 dda6 dda7 h raa cab cda rda raa rda dda8 dab1 dab2 rab daa1 daa2 ba0 caa rab activate command for bank a write command for bank a write command for bank d activate command for bank d precharge command for bank a activate command for bank a precharge command for bank d write command for bank a l hi-z dda4
preliminary data sheet m13394ej3v0ds00 61 m m m m pd 45256441, 45256841, 45256163 13.16 read and write (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq activate command for bank a read command for bank a write command for bank a 0-clock latency 2-clock latency read command for bank a t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 dab1 dab2 qac1 qac2 qac4 h raa cac cab dab4 ba0 caa write latency = 0 raa word masking l hi-z hi-z at the end of wrap function
preliminary data sheet m13394ej3v0ds00 62 m m m m pd 45256441, 45256841, 45256163 read and write (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 dab1 dab2 qac1 qac2 h raa cac cab dab4 caa raa ba0 activate command for bank a read command for bank a write command for bank a 0-clock latency read command for bank a word masking write latency = 0 l hi-z hi-z at the end of wrap function 2-clock latency
preliminary data sheet m13394ej3v0ds00 63 m m m m pd 45256441, 45256841, 45256163 13.17 interleaved column read cycle (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z aa1 aa2 aa3 aa4 da1 da2 dc1 dc2 dd1 dd2 dd3 dd4 h raa rda ab1 ab2 db1 db2 ba0 raa rda caa cda cdb cdc cab cdd activate command for bank a activate command for bank d read command for bank d read command for bank d read command for bank d read command for bank a read command for bank d precharge command for bank a precharge command for bank d read command for bank a
preliminary data sheet m13394ej3v0ds00 64 m m m m pd 45256441, 45256841, 45256163 interleaved column read cycle (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z aa1 aa2 aa3 aa4 da1 da2 dc1 dc2 ab3 ab4 h ab1 ab2 db1 db2 raa rda ba0 raa cab cdc rda cda caa activate command for bank a activate command for bank d read command for bank d read command for bank d read command for bank d read command for bank a precharge command for bank d precharge command for bank a read command for bank a cdb
preliminary data sheet m13394ej3v0ds00 65 m m m m pd 45256441, 45256841, 45256163 13.18 interleaved column write cycle (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z aa1 aa2 aa3 aa4 ba1 ba2 bc1 bc2 bd1 bd2 bd3 bd4 h raa rba ab1 ab2 bb1 bb2 raa rba caa cba cbb cbc cab cbd ba1 activate command for bank a write command for bank a activate command for bank b write command for bank b write command for bank a precharge command for bank a precharge command for bank b write command for bank b write command for bank b write command for bank b t dpl t dpl
preliminary data sheet m13394ej3v0ds00 66 m m m m pd 45256441, 45256841, 45256163 interleaved column write cycle (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z aa1 aa2 aa3 aa4 ba1 ba2 bc1 bc2 bd1 bd2 h ab1 ab2 bb1 bb2 raa rba raa cab cbc rba cba cbb caa cbd bd3 bd4 activate command for bank a write command for bank a activate command for bank b write command for bank b write command for bank a precharge command for bank a precharge command for bank b write command for bank b write command for bank b write command for bank b ba1
preliminary data sheet m13394ej3v0ds00 67 m m m m pd 45256441, 45256841, 45256163 13.19 auto precharge after read burst (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h ba1 rdb rac rda raa raa cab caa rdb cda rda cac cdb rac hi-z activate command for bank a activate command for bank d read command for bank a read with auto precharge command for bank d read with auto precharge command for bank a auto precharge start for bank d read with auto precharge command for bank d auto precharge start for bank a auto precharge start for bank d activate command for bank a read with auto precharge command for bank a activate command for bank d
preliminary data sheet m13394ej3v0ds00 68 m m m m pd 45256441, 45256841, 45256163 auto precharge after read burst (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h rdb raa raa cab caa rdb cda rda cdb hi-z ba1 rda activate command for bank a activate command for bank d read command for bank a read with auto precharge command for bank d activate command for bank d read with auto precharge command for bank a auto precharge start for bank a read with auto precharge command for bank d auto precharge start for bank d
preliminary data sheet m13394ej3v0ds00 69 m m m m pd 45256441, 45256841, 45256163 13.20 auto precharge after write burst (1/2) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq activate command for bank a write command for bank a activate command for bank d activate command for bank d write with auto precharge command for bank d write with auto precharge command for bank d write with auto precharge command for bank a auto precharge start for bank d auto precharge start for bank a auto precharge start for bank d activate command for bank a write with auto precharge command for bank a t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h rdb rac rda raa raa cab caa rdb cda rda cac cdb rac ba1 hi-z
preliminary data sheet m13394ej3v0ds00 70 m m m m pd 45256441, 45256841, 45256163 auto precharge after write burst (2/2) (burst length = 4, /cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h rdb raa raa cab caa rdb cda rda cdb rda ba1 hi-z activate command for bank a write command for bank a activate command for bank d write with auto precharge command for bank d write with auto precharge command for bank a auto precharge start for bank d auto precharge start for bank a activate command for bank d write with auto precharge command for bank d
preliminary data sheet m13394ej3v0ds00 71 m m m m pd 45256441, 45256841, 45256163 13.21 full page read cycle (1/2) (/cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t7 tn tn + 1tn + 2tn + 3tn + 4tn + 5tn + 6tn + 7tn + 8tn + 9tn + 10 tn + 11 tn + 12 tn + 13 h raa rda rdb raa rda cda caa rdb aa aa+1 aa+2 aa-2 aa-1 aa aa+1 da da+1 da+2 da+3 da+4 da+5 da+6 activate command for bank a read command for bank a activate command for bank d read command for bank d burst stop command precharge command for bank d activate command for bank d t6 ba1 l hi-z
preliminary data sheet m13394ej3v0ds00 72 m m m m pd 45256441, 45256841, 45256163 full page read cycle (2/2) (/cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 tn tn + 1tn + 2tn + 3tn + 4tn + 5tn + 6tn + 7tn + 8tn + 9tn + 10 tn + 11 tn + 12 l h raa rda rdb raa rda cda caa rdb aa aa+1 aa-3 aa-2 aa-1 aa aa+1 da da+1 da+2 da+3 da+4 da+5 precharge command for bank d activate command for bank a read command for bank a activate command for bank d read command for bank d burst stop command activate command for bank d hi-z ba1
preliminary data sheet m13394ej3v0ds00 73 m m m m pd 45256441, 45256841, 45256163 13.22 full page write cycle (1/2) (/cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 tn tn + 1tn + 2tn + 3tn + 4tn + 5tn + 6tn + 7tn + 8tn + 9tn + 10 tn + 11 tn + 12 tn + 13 tn + 14 tn + 15 h raa rda rdb raa rda cda caa rdb aa aa+1 aa+2 aa-2 aa-1 aa aa+1 da da+1 da+2 da+3 da+4 da+5 ba1 precharge command for bank d activate command for bank a write command for bank a activate command for bank d write command for bank d burst stop command activate command for bank d l hi-z
preliminary data sheet m13394ej3v0ds00 74 m m m m pd 45256441, 45256841, 45256163 full page write cycle (2/2) (/cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 tn tn + 1tn + 2tn + 3tn + 4tn + 5tn + 6tn + 7tn + 8tn + 9tn + 10 tn + 11 tn + 12 tn + 13 h raa rda rdb raa rda cda caa rdb aa aa+1 aa+2 aa+3 aa-1 aa aa+1 da da+1 da+2 da+3 da+4 da+5 precharge command for bank d activate command for bank a write command for bank a activate command for bank d burst is not completed in the full page mode write command for bank d burst stop command activate command for bank d ba1 l hi-z
preliminary data sheet m13394ej3v0ds00 75 m m m m pd 45256441, 45256841, 45256163 13.23 byte write operation (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add ldqm t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 udqm ba1 dq lower dq upper activate command for bank d read command for bank d u-byte not read l-byte not write u-byte not write l-byte not write
preliminary data sheet m13394ej3v0ds00 76 m m m m pd 45256441, 45256841, 45256163 13.24 burst read and single write (option) (burst length = 4, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h hi-z dq ba1 activate command for bank d read command for bank d single write command for bank d single write command for bank d read command for bank d single write command for bank d qa1 qa2 qa3 qa4 d1 qb1 qb2 qb4 d2
preliminary data sheet m13394ej3v0ds00 77 m m m m pd 45256441, 45256841, 45256163 13.25 full page random column read (burst length = full page, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h hi-z raa cac cdb cab rda rda cdc raa ba1 caa cda qaa1 qda1 qab1 qab2 qdb1 qdb2 qac1 qac2 qac3 qdc1 qdc2 qdc3 activate command for bank a activate command for bank d read command for bank a read command for bank d read command for bank a read command for bank d read command for bank a read command for bank d precharge command for bank d (pre termination of burst) hi-z t rcd t rrd t rcd h
preliminary data sheet m13394ej3v0ds00 78 m m m m pd 45256441, 45256841, 45256163 13.26 full page random column write (burst length = full page, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h hi-z raa cac cdb cab rda rda cdc raa ba1 caa cda daa1 dda1 dab1 dab2 ddb1 ddb2 dac1 dac2 dac3 ddc1 ddc2 ddc3 ddc4 precharge command for bank d (pre termination of burst) activate command for bank a activate command for bank d write command for bank a write command for bank d write command for bank a write command for bank d write command for bank a write command for bank d t rcd t rrd t rcd
preliminary data sheet m13394ej3v0ds00 79 m m m m pd 45256441, 45256841, 45256163 13.27 pre (precharge) termination of burst (1/2) (burst length = 8, /cas latency = 2) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h ba1 hi-z raa rab caa raa rab cab daa1 daa2 daa3 daa4 daa5 qab1 qab2 qab3 qab4 qab5 activate command for bank a activate command for bank a write command for bank a pre termination of burst pre termination of burst precharge command for bank a activate command for bank a read command for bank a precharge command for bank a hi-z write masking rac rac t rcd t dpl t rp t ras t ras
preliminary data sheet m13394ej3v0ds00 80 m m m m pd 45256441, 45256841, 45256163 pre (precharge) termination of burst (2/2) (burst length = 8, /cas latency = 3) clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z h ba1 raa rab caa raa rab cab daa1 daa2 daa3 qab1 qab2 qab3 qab4 hi-z activate command for bank a activate command for bank a write command for bank a pre termination of burst precharge command for bank a precharge command for bank a activate command for bank a read command for bank a pre termination of burst daa4 daa5 write mask rac rac t rcd t rp t ras t dpl t ras
preliminary data sheet m13394ej3v0ds00 81 m m m m pd 45256441, 45256841, 45256163 14. package drawing 54pin plastic tsop (ii) (400mil) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. a 22.62 max. 0.891 max. b 0.91 max. 0.036 max. j 0.800.20 0.031 +0.009 C0.008 k 0.145 0.0060.001 l 0.500.10 0.020 +0.004 C0.005 m 0.13 0.005 n 0.10 0.004 +0.025 C0.015 c 0.80 (t.p.) 0.031 (t.p.) d 0.32 0.0130.003 e 0.100.05 0.0040.002 f 1.20 max. 0.048 max. g 1.00 0.039 h 11.760.20 0.4630.008 i 10.160.10 0.4000.004 s54g5-80-9jf p3 +0.08 C0.07 +7 C3 3 +7 C3 m 54 28 127 p a g cn b m d l k j h i e f detail of lead end
preliminary data sheet m13394ej3v0ds00 82 m m m m pd 45256441, 45256841, 45256163 15. recommended soldering conditions please consult with our sales offices for soldering conditions of the m pd45256 xxx. type of surface mount device m pd45256 xxxg5: 54-pin plastic tsop (ii) ( 400 mil) 16. revision history edition / page description date this edition previous edition type of revision location 3rd edition / p.15 p.15 modification 4.3 cke truth table (power down) apr. 1999 p.19 p.19 modification 4.5 command truth table for cke (power down) p.35 p.35 modification i cc1 , i cc4 , i cc5 , i cc6 p.37 p.37 modification note 1. output load p.50 p.50 modification timing chart (power down mode exit) p.77 p.77 modification timing chart (precharge command for bank d)
preliminary data sheet m13394ej3v0ds00 83 m m m m pd 45256441, 45256841, 45256163 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd4 5 2 5 6441 , 4 5 2 5 6841 , 4 5 2 5 6163 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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